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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1997 jul 01 integrated circuits tda837x family i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors
1997 jul 01 2 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family features available in all ics: vision if amplifier with high sensitivity and good figures for differential phase and gain pll demodulator for the if signal alignment-free sound demodulator flexible source selection with a cvbs input for the internal signal and y/c or cvbs input for the external signal audio switch the output signal of the cvbs (y/c) switch is externally available integrated chrominance trap and band-pass filters (auto-calibrated) luminance delay line integrated a symmetrical peaking circuit in the luminance channel black stretching of non-standard cvbs or luminance signals rgb control circuit with black current stabilization and white point adjustment linear rgb inputs and fast blanking horizontal synchronization with two control loops and alignment-free horizontal oscillator slow start and slow stop of the horizontal drive pulses vertical count-down circuit vertical driver optimized for dc-coupled vertical output stages i 2 c-bus control of various functions low dissipation small amount of peripheral components compared with competition ics. general description the various versions of the tda837x series are i 2 c-bus controlled single-chip tv processors which are intended to be applied in pal/ntsc (tda8374 and tda8375) and ntsc (tda8373 and tda8377) television receivers. all ics are available in an sdip56 package and some versions are also available in a qfp64 package. the ics are pin compatible so that with one application board ntsc and pal/ntsc (or multistandard together with the secam decoder tda8395) receivers can be built. functionally this ic series is split in to 2 categories: versions intended to be used in economy tv receivers with all basic functions versions with additional functions such as e-w geometry control, horizontal and vertical zoom function and yuv interface which are intended for tv receivers with 110 picture tubes. the various type numbers are given in table 1. the detailed differences between the various ics are given in table 2. table 1 tv receiver versions tv receivers sdip56 package qfp64 package economy mid/high end economy mid/high end pal only tda8374b - tda8374bh - pal/ntsc (secam) tda8374 and tda8374a tda8375 and tda8375a tda8374ah tda8375ah ntsc tda8373 tda8377 and tda8377a --
1997 jul 01 3 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family table 2 differences between the various ics quick reference data circuits ic version (tda) 8373 8374 8374a(h) 8374b(h) 8375 8375a(h) 8377 8377a multistandard if - x -- xx -- automatic volume levelling (avl) xx - --- -- pal decoder - x x xxx -- secam interface - x x xxx -- ntsc decoder x x x x x x x x colour matrix pal/ntsc (japan) - x x xxx -- colour matrix ntsc (usa/japan) x - - --- xx yuv interface -- - - xx xx horizontal geometry -- - - xx xx horizontal and vertical zoom -- - - xx xx symbol parameter conditions min. typ. max. unit supplies v p supply voltage - 8.0 - v i p supply current - 110 - ma input voltages v 48,49(rms) video if ampli?ers sensitivity (rms value) - 70 -m v v 1(rms) sound if ampli?ers sensitivity (rms value) - 1.0 - mv v 2(rms) external audio input voltage (rms value) - 500 - mv v 11(p-p) external cvbs/y input voltage (peak-to-peak value) - 1.0 - v v 10(p-p) external chrominance input voltage (burst amplitude) (peak-to-peak value) - 0.3 - v v 23-25(p-p) rgb input voltage (peak-to-peak value) - 0.7 - v output signals v 6(p-p) if video output voltage (peak-to-peak value) - 2.5 - v i 54 tuner agc output current range 0 - 5ma v ovsw output signal level of video switch (peak-to-peak value) - 1.0 - v v 30(p-p) - (r - y) output voltage (peak-to-peak value) - 525 - mv
1997 jul 01 4 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family ordering information v 29(p-p) - (b - y) output voltage (peak-to-peak value) - 675 - mv v 28(p-p) luminance output voltage (peak-to-peak value) - 1.4 - v v 19-21(p-p) rgb output signal amplitudes (peak-to-peak value) - 2.0 - v i 40 horizontal output current - 10 - ma i 46,47(p-p) vertical output current (peak-to-peak value) - 1 - ma i 45(peak) e-w output current (peak value) tda8375a, tda8377a, tda8375 and tda8377 - 1.2 - ma type number package name description version tda837xa sdip56 plastic shrink dual in-line package; 56 leads (600 mil) sot400-1 tda837xh qfp64 plastic quad ?at package; 64 leads (lead length 1.95 mm); body 14 20 2.7 mm; high stand-off height sot319-1 symbol parameter conditions min. typ. max. unit
1997 jul 01 5 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family block diagram o ok, full pagewidth mgk286 rgb matrix rgb input and switch g - y matrix and sat control ntsc decoder rgb control and output delay and peaking black stretcher vertical sync separator trap black current stabilizer vertical geometry horizontal/ vertical divider sync separator and 1st loop vco and control 2nd loop and horizontal output control dacs 1 8 bits 14 6 bits 1 4 bits 23 31 32 29 30 43 14 44 12 37 ref 8 7 53 9 42 41 54 34 36 33 616 11 10 38 17 13 39 3 3.6 mhz 3 21 18 52 51 22 20 46 50 40 47 19 white point bri tda8373 sat ref b - y r - y hue contr 24 25 26 filter tuning band-pass sw sw 56 1 55 2 45 15 49 5 mute vol sw cvbs y/c switch pre-amplifier and mute mute ident adj tuner take-over point + 8 v afc video amplifier and mute video identification agc for if and tuner i 2 c-bus transceiver 48 4 3 vif amplifier and pll demodulator vco adjustment cvbs switch avl and switch and volume control afc pll demodulator sound trap sound band-pass limiter fig.1 block diagram of bus-controlled economy ntsc tv-processor tda8373. the tda8373 is only supplied in an sdip package.
1997 jul 01 6 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family o k, full pagewidth mgk287 rgb matrix rgb input and switch g - y matrix and sat control pal/ntsc decoder rgb control and output delay and peaking black stretcher vertical sync separator trap black current stabilizer vertical geometry horizontal/ vertical divider sync separator and 1st loop vco and control 2nd loop and horizontal output control dacs 1 8 bits 14 6 bits 1 4 bits 23 31 32 29 30 43 14 44 12 37 ref 8 7 53 9 42 41 54 34 (51) 35 36 33 616 11 10 38 17 13 39 3 3.6 mhz 3 21 18 52 51 22 20 46 50 40 47 19 white point bri tda8374 sat ref b - y r - y hue contr 24 25 26 4.4 mhz filter tuning band-pass sw sw 56 1 55 2 45 15 49 5 mute vol sw cvbs y/c switch pre-amplifier and mute mute ident adj tuner take-over point pol + 8 v afc pol video amplifier and mute video identification agc for if and tuner i 2 c-bus transceiver 48 4 3 vif amplifier and pll demodulator vco adjustment cvbs switch avl and switch and volume control afc pll demodulator sound trap tda4665 sound band-pass limiter fig.2 block diagram of bus-controlled economy pal/ntsc tv processor tda8374. for most pins the qfp64 pinning is not indicated.
1997 jul 01 7 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family o ok, full pagewidth mgk288 rgb matrix rgb input and switch g - y matrix and sat control pal/ntsc decoder rgb control and output delay plus peaking plus coring black stretcher vertical sync separator trap black current stabilizer vertical geometry horizontal/ vertical divider sync separator and 1st loop vco and control 2nd loop and horizontal output control dacs 1 8 bits 18 6 bits 1 4 bits (35) 23 (47) 31 (40) 28 (39) 27 (48) 32 (45) 29 (46) 30 43 (59) 14 (25,26) 44 (60,61) 12 (22,23) 37 (53) ref 8 (18) 7 (17) 53 (6) 9 (19) 42 (58) 41 (57) 40 (56) 54 (7) (50) 34 (51) 35 (52) 36 (49) 33 (16) 6 (28) 16 (21) 11 (20) 10 (54) 38 (29) 17 (24) 13 (55) 39 3 3.6 mhz 3 (33) 21 (30) 18 (5) 52 (4) 51 (34) 22 (32) 20 (63) 46 (3) 50 e-w geometry (62) 45 (64) 47 (31) 19 white point bri tda8375 sat ref b - y r - y hue contr (36) 24 (37) 25 (38) 26 4.4 mhz filter tuning band-pass sw sw 56 (9) 1 (10) 55 (8) 2 (11) 15 (27) 49 (2) 5 (15) mute vol sw cvbs y/c switch pre-amplifier and mute mute ident adj tuner take-over point pol + 8 v afc pol video amplifier and mute video identification agc for if and tuner i 2 c-bus transceiver 48 (1) 4 (14) 3 (13) vif amplifier and pll demodulator vco adjustment cvbs switch switch and volume control afc pll demodulator sound trap tda4665 sound band-pass limiter fig.3 block diagram of bus-controlled economy pal/ntsc tv processor tda8375.
1997 jul 01 8 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family f ull pagewidth mgk289 rgb matrix rgb input and switch g - y matrix and sat control ntsc decoder rgb control and output delay plus peaking plus coring black stretcher vertical sync separator trap black current stabilizer vertical geometry horizontal/ vertical divider sync separator and 1st loop vco and control 2nd loop and horizontal output control dacs 1 8 bits 18 6 bits 1 4 bits 23 31 28 27 32 29 30 43 14 44 12 37 ref 8 7 53 9 42 41 40 54 34 36 33 616 11 10 38 17 13 39 3 3.6 mhz 3 21 18 52 51 22 20 46 50 e-w geometry 45 47 19 white point bri tda8377 sat ref b - y r - y hue contr 24 25 26 filter tuning band-pass sw sw 56 1 55 2 15 49 5 mute vol sw cvbs y/c switch pre-amplifier and mute mute ident adj tuner take-over point + 8 v afc video amplifier and mute video identification agc for if and tuner i 2 c-bus transceiver 48 4 3 vif amplifier and pll demodulator vco adjustment cvbs switch switch and volume control afc pll demodulator sound trap sound band-pass limiter fig.4 block diagram of bus-controlled economy ntsc tv processor tda8377. the tda8377 is only supplied in an sdip package.
1997 jul 01 9 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family pinning symbol pin description sdip56 qfp64 sif 1 10 sound if input audi 2 11 external audio input vco1 3 13 if vco 1 tuned circuit vco2 4 14 if vco 2 tuned circuit pll 5 15 pll loop ?lter ifvo 6 16 if video output scl 7 17 serial clock input (i 2 c-bus) sda 8 18 serial data input/output (i 2 c-bus) dec bg 9 19 band gap decoupling chroma 10 20 chrominance input cvbs/y 11 21 cvbs/y input v p1 12 22 and 23 main supply voltage (+8 v) cvbs int 13 24 internal cvbs input gnd1 14 25 and 26 ground audo 15 27 audio output dec ft 16 28 decoupling ?lter tuning cvbs ext 17 29 external cvbs input blkin 18 30 black current input bo 19 31 blue output go 20 32 green output ro 21 33 red output bclin 22 34 beam current input ri 23 35 red input gi 24 36 green input bi 25 37 blue input rgbin 26 38 rgb insertion input yin 27 (2) 39 luminance input yout 28 40 luminance output byo 29 45 (b - y) output ryo 30 46 (r - y) output ryi 31 47 (r - y) input byi 32 48 (b - y) input sec ref 33 (1) 49 secam reference output xtal1 34 50 3.58 mhz crystal connection xtal2 35 (1) 51 4.43 mhz crystal connection lfbp 36 52 loop ?lter burst phase detector v p2 37 53 horizontal oscillator supply voltage (+8 v) cvbso 38 54 cvbs output
1997 jul 01 10 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family notes 1. in the tda8373 and tda8377 pin 35 (4.43 mhz crystal) is internally connected and pin 33 is just a subcarrier output which can be used as a reference signal for comb filter ics. 2. in the tda8373 and tda8374 the following pins are different (sdip56): pin 27: not connected; pin 45: avl capacitor. blph 39 55 black peak hold capacitor hout 40 56 horizontal drive output fbi/sco 41 57 ?yback input and sandcastle output ph2 42 58 phase 2 ?lter/protection ph1 43 59 phase 1 ?lter gnd2 44 60 and 61 ground 2 ewd 45 (2) 62 east-west drive output vdob 46 63 vertical drive output b vdoa 47 64 vertical drive output a ifin1 48 1 if input 1 ifin2 49 2 if input 2 eht/pro 50 3 eht/overvoltage protection input vsaw 51 4 vertical sawtooth capacitor i ref 52 5 reference current input dec agc 53 6 agc decoupling capacitor agcout 54 7 tuner agc output audeem 55 8 audio deemphasis dec 56 9 decoupling sound demodulator i.c. - 12 internally connected i.c. - 41 internally connected i.c. - 42 internally connected i.c. - 43 internally connected i.c. - 44 internally connected symbol pin description sdip56 qfp64
1997 jul 01 11 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.5 pin configuration (sdip56). handbook, halfpage tda837x mgk284 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 55 56 54 53 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 27 28 sif audi vco1 vco2 pll ifvo scl sda dec bg chroma cvbs/y v p1 cvbs int gnd1 audo dec ft cvbs ext blkin bo go ro bclin ri gi bi rgbin yin yout dec audeem agcout dec agc i ref vsaw eht/pro ifin2 ifin1 vdoa vdob ewd gnd2 ph1 ph2 fbi/sco hout blph cvbso v p2 lfbp xtal2 xtal1 sec ref byi ryi ryo byo
1997 jul 01 12 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.6 pin configuration (qfp64). handbook, full pagewidth tda837xh mgk285 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 byi ryi ryo byo i.c. i.c. i.c. i.c. yout yin rgbin bi gi ri bclin ro ifin1 ifin2 eht/pro vsaw i ref dec agc agcout audeem dec sif audi i.c. vco1 vco2 pll ifvo 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 vdoa vdob ewd gnd2 gnd2 ph1 ph2 fbi/sco hout blph cvbso v p2 lfbp xtal2 xtal1 sec ref scl sda dec bg chroma cvbs/y v p1 v p1 cvbs int gnd1 gnd1 audo dec ft cvbs ext blkin bo go 49
1997 jul 01 13 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family functional description vision if ampli?er the if amplifier contains 3 ac-coupled control stages with a total gain control range which is higher than 66 db. the sensitivity of the circuit is comparable with that of modern if-ics. the video signal is demodulated by a pll carrier regenerator. this circuit contains a frequency detector and a phase detector. during acquisition the frequency detector will tune the vco to the correct frequency. the initial adjustment of the oscillator is realized via the i 2 c-bus. the switching, between secam l and l, can also be realized via the i 2 c-bus. after lock-in the phase detector controls the vco so that a stable phase relationship between the vco and the input signal is achieved. the vco operates at twice the if frequency. the reference signal for the demodulator is obtained by using a frequency divider circuit. the afc output is obtained by using the vco control voltage of the pll and can be read via the i 2 c-bus. for fast search tuning systems the window of the afc can be increased by a factor of 3. the setting is realized with the afw bit. depending on the device type the agc detector operates on top-sync level (single standard versions) or on top-sync and top-white level (multistandard versions). the demodulation polarity is switched via the i 2 c-bus. the agc detector time constant capacitor is connected externally. this is mainly because of the flexibility of the application. the time constant of the agc system during positive modulation is rather long, this is to avoid visible variations of the signal amplitude. to improve the speed of the agc system, a circuit has been included which detects whether the agc detector is activated every frame period. when, during 3 frame periods, no action is detected the speed of the system is increased. for signals without peak-white information the system switches automatically to a gated black level agc. because a black level clamp pulse is required for this method of operation the circuit will only switch to black level agc in the internal mode. the circuits contain a second fast video identification circuit which is independent of the synchronization identification circuit. consequently, search tuning is also possible when the display section of the receiver is used as a monitor. however, this identification circuit cannot be made as sensitive as the slower sync identification circuit (sl) and it is recommended to use both identification outputs to obtain a reliable search system. the identification output is applied to the tuning system via the i 2 c-bus. the input of the identification circuit is connected to pin 13, the internal cvbs input (see fig.1). this has the advantage that the identification circuit can also be made operative when a scrambled signal is received [descrambler connected between the if video output (pin 6) and pin 13]. a second advantage is that the identification circuit can be used when the if amplifier is not used (e.g. with built-in satellite tuners). the video identification circuit can also be used to identify the selected cbvs or y/c signal. the switching between the two modes can be realized with bit vim. video switches the circuit has two cvbs inputs (cvbs int and cvbs ext ) and a y/c input. when the y/c input is not required pin 11 can be used as the third cvbs input. the switch configuration is illustrated in fig.7. the selection of the various sources is made via the i 2 c-bus. the output signal of the cvbs switch is externally available and can be used to drive the teletext decoder, the secam add-on decoder and a comb filter. in applications with comb filters a y/c input is only possible when additional switches are added. in applications without comb filters the y/c input signal can be switched to the cvbs output.
1997 jul 01 14 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.7 configuration cvbs switch and interfacing of video identification. handbook, full pagewidth mgk301 video identification s0 vim ident tda837x cvbs int 13 s0 s5 s1 cvbs ext 17 s1 s6 s2 cvbs/y 11 s3 s7 s4 chroma cvbso 10 38 to luminance/ sync processing to chrominance processing s8 + sound circuit the sound band-pass and trap filters have to be connected externally. the filtered intercarrier signal is fed to a limiter circuit and is demodulated by a pll demodulator. this pll circuit automatically tunes to the incoming carrier signal, hence no adjustment is required. the volume is controlled via the i 2 c-bus. the de-emphasis capacitor has to be connected externally. the non-controlled audio signal can be obtained from this pin (pin 55) (via a buffer stage). the fm demodulator can be muted via the i 2 c-bus. this function can be used to switch-off the sound during a channel change so that high output peaks are prevented (also on the de-emphasis output). the tda8373 and tda8374 contain an automatic volume levelling (avl) circuit which automatically stabilizes the audio output signal to a certain level which can be set by the user via the volume control. this function prevents big audio output fluctuations due to variations of the modulation depth of the transmitter. the avl function can be activated via the i 2 c-bus. synchronization circuit the sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. these pulses are fed to the slicing stage which operates at 50% of the amplitude. the separated sync pulses are fed to the first phase detector and to the coincidence detector. the coincidence detector is used to detect whether the line oscillator is synchronized and can also be used for transmitter identification. the circuit can be made less sensitive by using the stm bit. this mode can be used during search tuning to ensure that the tuning system will not stop at very weak input signals. the first pll has a very high static steepness so that the phase of the picture is independent of the line frequency. the line oscillator operates at twice the line frequency. the oscillator capacitor is internal. because of the spread of internal components an automatic calibration circuit has been added to the ic. the circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder.
1997 jul 01 15 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family this results in a free-running frequency which deviates less than 2% from the typical value. when the ic is switched on the horizontal output signal is suppressed and the oscillator is calibrated as soon as all subaddress bytes have been sent. when the frequency of the oscillator is correct the horizontal drive signal is switched on. to obtain a smooth switching on and switching off behaviour of the horizontal output stage the horizontal output frequency is doubled during switch-on and switch-off (slow start/stop). during that time the duty cycle of the output pulse has such a value that maximum safety is obtained for the output stage. to protect the horizontal output transistor, the horizontal drive is immediately switched off (via the slow stop procedure) when a power-on reset is detected. the drive signal is switched on again when the normal switch-on procedure is followed, i.e. all subaddress bytes must be sent and, after calibration, the horizontal drive signal will be released again via the slow start procedure. when the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated. the circuit has a second control loop to generate the drive pulses for the horizontal driver stage. the horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched on during the flyback time. adjustments can be made to the horizontal shift, vertical shift, vertical slope, vertical amplitude and the s-correction via the i 2 c-bus. in the tda8375a, tda8377a, tda8375 and tda8377 the e-w drive can also be adjusted via the i 2 c-bus. the tda8375 and tda8377 have a flexible zoom adjustment possibility for the vertical and horizontal deflection. when the horizontal scan is reduced to display 4 : 3 pictures on a 1 6 : 9 picture tube an accurate video blanking can be switched on to obtain well defined edges on the screen. the geometry processor has a differential output for the vertical drive signal and a single-ended output for the e-w drive (tda8375a, tda8377a, tda8375 and tda8377). overvoltage conditions (x-ray protection) can be detected via the eht tracking pin. when an overvoltage condition is detected the horizontal output drive signal will be switched off via the slow stop procedure. however, it is also possible that the drive is not switched off and that just a protection indication is given in the i 2 c-bus output byte. the choice is made via the input bit prd. the ics have a second protection input on the phase-2 filter capacitor pin. when this input is activated the drive signal is switched off immediately (without slow stop) and switched on again via the slow start procedure. for this reason this protection input can be used as flash protection. the drive pulses for the vertical sawtooth generator are obtained from a vertical countdown circuit. this countdown circuit has various windows depending on the incoming signal (50 or 60 hz and standard or non-standard). the countdown circuit can be forced in various modes via the i 2 c-bus. to obtain short switching times of the countdown circuit during a channel change the divider can be forced in the search window using the ncin bit. the vertical deflection can be set in the de-interlace mode via the i 2 c-bus. to avoid damage of the picture tube when the vertical deflection fails, the guard output current of the tda8350 and tda8351 can be supplied to the beam current limiting input. when a failure is detected the rgb outputs are blanked and a bit is set (ndf) in the status byte of the i 2 c-bus. when no vertical deflection output stage is connected this guard circuit will also blank the output signals. this can be overruled using the evg bit. chrominance and luminance processing the circuit contains a chrominance band-pass and trap circuit. the filters are realized by using gyrator circuits. they are automatically calibrated by comparing the tuning frequency with the crystal frequency of the decoder. the luminance delay line and the delay for the peaking circuit are also realized by using gyrator circuits. the centre frequency of the chrominance band-pass filter is 10% higher than the subcarrier frequency. this compensates for the high frequency attenuation of the if saw filter. during secam reception the centre frequency of the chrominance trap is reduced to obtain a better suppression of the secam carrier frequencies. all ics have a black stretcher circuit which corrects the black level for incoming video signals which have a deviation between the black level and the blanking level (back porch). the tda8375a, tda8377a, tda8375 and tda8377 have a defeatable coring function in the peaking circuit. some of the ics have a yuv interface so that picture improvement ics such as the tda9170 (contrast improvement), tda9177 (sharpness improvement) and tda4556 and tda4566 (cti) can be applied. when the tda4556 or tda4566 is applied it is possible to increase the gain of the luminance channel by using the gai bit in subaddress 03 so that the resulting rgb output signals will not be affected.
1997 jul 01 16 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family colour decoder depending on the ic type the colour decoder can decode ntsc signals (tda8373 and tda8377) or pal/ntsc signals (tda8374 and tda8375). the circuit contains an alignment-free crystal oscillator, a killer circuit and two colour difference demodulators. the 90 phase shift for the reference signal is made internally. the tda8373 and tda8377 contain an automatic colour limiting (acl) circuit which prevents over saturation occurring when signals with a high chroma-to-burst ratio are received. this acl function is also available in the tda8374 and tda8375, however, it is only active during the reception of ntsc signals. the tda8373 and tda8377 have a switchable colour difference matrix (via the i 2 c-bus) so that the colour reproduction can be adapted to the market requirements. in the tda8374 and tda8375 the colour difference matrix switches automatically between pal and ntsc, however, it is also possible to fix the matrix in the pal standard. the tda8374 and tda8375 can operate in conjunction with the secam decoder tda8395 so that an automatic multistandard decoder can be realized. the subcarrier reference output for the secam decoder can also be used as a reference signal for a comb filter. consequently, the reference signal is continuously available when pal or ntsc signals are detected and only present during the vertical retrace period when a secam signal is detected. which standard the tda8374 and tda8375 can decode depends on the external crystals. the crystal to be connected to pin 34 must have a frequency of 3.5 mhz (ntsc-m, pal-m or pal-n). pin 35 can handle crystals with a frequency of 4.4 and 3.5 mhz. because the crystal frequency is used to tune the line oscillator, the value of the crystal frequency must be communicated to the ic via the i 2 c-bus. it is also possible to use the ic in the so called 3-norma mode for south america. in that event one crystal must be connected to pin 35 and the other two to pin 34. switching between the 2 latter crystals must be performed externally. consequently, the search loop of the decoder must be controlled by the microcontroller. to prevent calibration problems of the horizontal oscillator the external switching between the two crystals should be performed when the oscillator is forced to pin 35. for a reliable calibration of the horizontal oscillator it is very important that the crystal indication bits (xa and xb) are not corrupted. for this reason the crystal bits can be read in the output bytes so that the software can check the i 2 c-bus transmission. rgb output circuit and black current stabilization the colour difference signals are matrixed with the luminance signal to obtain the rgb signals. linear amplifiers have been chosen for the rgb inputs so that the circuit is suited for signals that are input from the scart connector. the insertion blanking can be switched on or off using the ie1 bit. to ascertain whether the insertion pin has a (continuous) high level or not can be read via the in1 bit. the contrast and brightness control operate on internal and external signals. the output signal has an amplitude of approximately 2 v (black-to-white) at nominal input signals and nominal settings of the controls. to increase the flexibility of the ic it is possible to add osd and/or teletext signals directly at the rgb outputs. this insertion mode is controlled via the insertion input. the action to switch the rgb outputs to black has some delay which must be compensated for externally. the black current stabilization is realized by using a feedback from the video output amplifiers to the rgb control circuit. the black current of the 3 guns of the picture tube is internally measured and stabilized. the black level control is active during 4 lines at the end of the vertical blanking. the vertical blanking is adapted to the incoming cvbs signal (50 or 60 hz). when the flyback time of the vertical output stage is longer than the 60 hz blanking time, or when additional lines need to be blanked (e.g. for close captioning lines) the blanking can be increased to the same value as that of the 50 hz blanking. this can be set using the lbm bit. the leakage current is measured during the first line and, during the following 3 lines, the 3 guns are adjusted to the required level. the maximum acceptable leakage current is 100 m a. the nominal value of the black current is 10 m a. the ratio of the currents for the various guns automatically tracks with the white point adjustment so that the background colour is the same as the adjusted white point.
1997 jul 01 17 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family the input impedance of the black current measuring pin is 14 k w . to prevent the voltage on this pin exceeding the supply voltage during scan an internal protection diode has been included. when the tv receiver is switched on the black current stabilization circuit is not active, the rgb outputs are blanked and the beam current limiting input pin is short-circuited. only during the measuring lines will the outputs supply a voltage of 4.2 v to the video output stage to ascertain whether the picture tube is warming up. as soon as the current supplied to the measuring input exceeds a value of 190 m a the stabilization circuit will be activated. after a waiting time of approximately 0.8 s the blanking and beam current limiting input pins are released. the remaining switch-on behaviour of the picture is determined by the external time constant of the beam current limiting network. i 2 c-bus speci?cation table 3 slave address (8a) a6 a5 a4 a3 a2 a1 a0 r/w 1000101i/o the slave address is identical for all types. the subaddresses of the various types are slightly different. the list of subaddresses for each type is given in tables 4, 6, 8 and 10. s tart - up procedure read the status bytes until por = 0 and send all subaddress bytes. the horizontal output signal is switched on when the oscillator is calibrated. each time before the data in the ic is refreshed, the status bytes must be read. if por = 1, then the procedure given above must be carried out to restart the ic. when this procedure is not followed the horizontal frequency in the tda8374 and tda8375 may be incorrect after power-up or a power dip.
1997 jul 01 18 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family tda8373 valid subaddresses: 00 to 16 (subaddresses 04 to 07 are not used), subaddress fe is reserved for test purposes. auto-increment mode available for subaddresses. table 4 inputs table 5 output status bytes (note 1) note 1. x = dont care. function sub address data byte d7 d6 d5 d4 d3 d2 d1 d0 control 0 00 ina inb inc 0 foa fob 0 0 control 1 01 0 0 dl stb poc 0 1 1 hue 02 avl akb a5 a4 a3 a2 a1 a0 horizontal shift (hs) 03 vim gai a5 a4 a3 a2 a1 a0 vertical slope (vs) 08 ncin stm a5 a4 a3 a2 a1 a0 vertical amplitude (va) 09 vid lbm a5 a4 a3 a2 a1 a0 s-correction (sc) 0a 0 evg a5 a4 a3 a2 a1 a0 vertical shift (vsh) 0b sbl prd a5 a4 a3 a2 a1 a0 white point r 0c 0 0 a5 a4 a3 a2 a1 a0 white point g 0d 0 0 a5 a4 a3 a2 a1 a0 white point b 0e mat 0 a5 a4 a3 a2 a1 a0 peaking 0f 0000a3a2a1a0 brightness 10 rbl 0 a5 a4 a3 a2 a1 a0 saturation 11 ie1 0 a5 a4 a3 a2 a1 a0 contrast 12 afw ifs a5 a4 a3 a2 a1 a0 agc takeover 13 0 vsw a5 a4 a3 a2 a1 a0 volume control 14 sm fav a5 a4 a3 a2 a1 a0 adjustment if-pll 15 lfa a6 a5 a4 a3 a2 a1 a0 spare 16 00000000 output address d7 d6 d5 d4 d3 d2 d1 d0 00 por x x sl xpr cd2 cd1 cd0 01 ndf in1 x ifi afa afb sxa sxb 02 x x x ivw x id2 id1 id0
1997 jul 01 19 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family tda8374, tda8374ah and tda8374bh valid subaddresses: 00 to 16 (subaddresses 04 to 07 are not used), subaddress fe is reserved for test purposes. auto-increment mode available for subaddresses. table 6 inputs (notes 1 and 2) notes 1. the avl and mod bit are not available in the tda8374a. 2. in the tda8374b the avl and mod bit is also missing and the cm0 to cm2 and cd0 to cd2 bits have less possibilities because this ic can only decode pal or pal/secam signals (when the tda8395 is applied). table 7 output status bytes (note 1) note 1. x = dont care. function sub address data byte d7 d6 d5 d4 d3 d2 d1 d0 control 0 00 ina inb inc 0 foa fob xa xb control 1 01 forf fors dl stb poc cm2 cm1 cm0 hue 02 avl akb a5 a4 a3 a2 a1 a0 horizontal shift (hs) 03 vim gai a5 a4 a3 a2 a1 a0 vertical slope (vs) 08 ncin stm a5 a4 a3 a2 a1 a0 vertical amplitude (va) 09 vid lbm a5 a4 a3 a2 a1 a0 s-correction (sc) 0a 0 evg a5 a4 a3 a2 a1 a0 vertical shift (vsh) 0b sbl prd a5 a4 a3 a2 a1 a0 white point r 0c 0 0 a5 a4 a3 a2 a1 a0 white point g 0d 0 0 a5 a4 a3 a2 a1 a0 white point b 0e mat 0 a5 a4 a3 a2 a1 a0 peaking 0f 0000a3a2a1a0 brightness 10 rbl 0 a5 a4 a3 a2 a1 a0 saturation 11 ie1 0 a5 a4 a3 a2 a1 a0 contrast 12 afw ifs a5 a4 a3 a2 a1 a0 agc takeover 13 mod vsw a5 a4 a3 a2 a1 a0 volume control 14 sm fav a5 a4 a3 a2 a1 a0 adjustment if-pll 15 lfa a6 a5 a4 a3 a2 a1 a0 spare 16 00000000 output address d7 d6 d5 d4 d3 d2 d1 d0 00 por fsi x sl xpr cd2 cd1 cd0 01 ndf in1 x ifi afa afb sxa sxb 02 x x x ivw x id2 id1 id0
1997 jul 01 20 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family tda8375 and tda8375ah valid subaddresses: 00 to 16, subaddress fe is reserved for test purposes. auto-increment mode available for subaddresses. table 8 inputs note 1. the vertical zoom byte and the hbl bit are active only in the tda8375. table 9 output status bytes (note 1) note 1. x = dont care. function sub address data byte d7 d6 d5 d4 d3 d2 d1 d0 control 0 00 ina inb inc 0 foa fob xa xb control 1 01 forf fors dl stb poc cm2 cm1 cm0 hue 02 hbl akb a5 a4 a3 a2 a1 a0 horizontal shift (hs) 03 vim gai a5 a4 a3 a2 a1 a0 e-w width (ew) 04 0 0 a5 a4 a3 a2 a1 a0 e-w parabola/width (pw) 05 0 0 a5 a4 a3 a2 a1 a0 e-w corner parabola (cp) 06 0 0 a5 a4 a3 a2 a1 a0 e-w trapezium (tc) 07 0 0 a5 a4 a3 a2 a1 a0 vertical slope (vs) 08 ncin stm a5 a4 a3 a2 a1 a0 vertical amplitude (va) 09 vid lbm a5 a4 a3 a2 a1 a0 s-correction (sc) 0a hco evg a5 a4 a3 a2 a1 a0 vertical shift (vsh) 0b sbl prd a5 a4 a3 a2 a1 a0 white point r 0c 0 0 a5 a4 a3 a2 a1 a0 white point g 0d 0 0 a5 a4 a3 a2 a1 a0 white point b 0e mat 0 a5 a4 a3 a2 a1 a0 peaking 0f 0000a3a2a1a0 brightness 10 rbl cor a5 a4 a3 a2 a1 a0 saturation 11 ie1 0 a5 a4 a3 a2 a1 a0 contrast 12 afw ifs a5 a4 a3 a2 a1 a0 agc takeover 13 mod vsw a5 a4 a3 a2 a1 a0 volume control 14 sm fav a5 a4 a3 a2 a1 a0 adjustment if-pll 15 lfa a6 a5 a4 a3 a2 a1 a0 vertical zoom (vx) (1) 16 0 0 a5 a4 a3 a2 a1 a0 output address d7 d6 d5 d4 d3 d2 d1 d0 00 por fsi x sl xpr cd2 cd1 cd0 01 ndf in1 x ifi afa afb sxa sxb 02 x x x ivw x id2 id1 id0
1997 jul 01 21 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family tda8377 and tda8377a valid subaddresses: 00 to 16, subaddress fe is reserved for test purposes. auto-increment mode available for subaddresses. table 10 inputs note 1. the vertical zoom byte and the hbl bit are active only in the tda8377. table 11 output status bytes (note 1) note 1. x = dont care. function sub address data byte d7 d6 d5 d4 d3 d2 d1 d0 control 0 00 ina inb inc 0 foa fob 0 1 control 1 01 0 0 dl stb poc 0 1 1 hue 02 hbl akb a5 a4 a3 a2 a1 a0 horizontal shift (hs) 03 vim gai a5 a4 a3 a2 a1 a0 e-w width (ew) 04 0 0 a5 a4 a3 a2 a1 a0 e-w parabola/width (pw) 05 0 0 a5 a4 a3 a2 a1 a0 e-w corner parabola (cp) 06 0 0 a5 a4 a3 a2 a1 a0 e-w trapezium (tc) 07 0 0 a5 a4 a3 a2 a1 a0 vertical slope (vs) 08 ncin stm a5 a4 a3 a2 a1 a0 vertical amplitude (va) 09 vid 0 a5 a4 a3 a2 a1 a0 s-correction (sc) 0a hco evg a5 a4 a3 a2 a1 a0 vertical shift (vsh) 0b sbl prd a5 a4 a3 a2 a1 a0 white point r 0c 0 0 a5 a4 a3 a2 a1 a0 white point g 0d 0 0 a5 a4 a3 a2 a1 a0 white point b 0e mat 0 a5 a4 a3 a2 a1 a0 peaking 0f 0000a3a2a1a0 brightness 10 rbl cor a5 a4 a3 a2 a1 a0 saturation 11 ie1 0 a5 a4 a3 a2 a1 a0 contrast 12 afw ifs a5 a4 a3 a2 a1 a0 agc takeover 13 0 vsw a5 a4 a3 a2 a1 a0 volume control 14 sm fav a5 a4 a3 a2 a1 a0 adjustment if-pll 15 lfa a6 a5 a4 a3 a2 a1 a0 vertical zoom (vx) (1) 16 0 0 a5 a4 a3 a2 a1 a0 output address d7 d6 d5 d4 d3 d2 d1 d0 00 por x x sl xpr cd2 cd1 cd0 01 ndf in1 x ifi afa afb sxa sxb 02 x x x ivw x id2 id1 id0
1997 jul 01 22 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family i nput control bits table 12 source select table 13 phase 1 ( j -1) time constant table 14 crystal indication table 15 forced ?eld frequency tda8374 and tda8375 note 1. when switched to this mode while locked to a 50 hz signal, the divider will only switch to forced 60 hz when an out-of-sync is detected in the horizontal pll. ina inb inc selected signals (decoder and audio) switch output 0 0 0 internal cvbs plus audio internal cvbs 0 0 1 external cvbs plus audio external cvbs 0 1 0 y/c plus external audio y/c (y plus c) 0 1 1 cvbs3 plus external audio cvbs3 1 0 0 y/c plus internal audio internal cvbs 1 1 0 y/c plus external audio external cvbs foa fob mode 0 0 normal 0 1 slow and gated 1 0 slow/fast and gated 1 1 fast xa xb crystal 0 0 two 3.6 mhz crystals 0 1 one 3.6 mhz crystal (pin 34) 1 0 one 4.4 mhz crystal (pin 35) 1 1 3.6 mhz and 4.4 mhz crystals (pins 34 and 35) forf fors field frequency 0 0 auto (60 hz when line not synchronized) 0 1 60 hz; note 1 1 0 keep last detected ?eld frequency 1 1 auto (50 hz when line not synchronized)
1997 jul 01 23 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family table 16 interlace table 17 standby table 18 synchronization mode table 19 colour decoder mode table 20 automatic volume levelling (tda8373 and tda8374) table 21 rgb blanking mode (tda8375 and tda8377) dl status 0 interlace 1 de-interlace stb mode 0 standby 1 normal poc mode 0 synchronization active 1 synchronization not active cm2 cm1 cm0 decoder mode 0 0 0 not forced, own intelligence, two crystals 0 0 1 forced crystal pin 34 (pal/ntsc) 0 1 0 forced crystal pin 34 (pal) 0 1 1 forced crystal pin 34 (ntsc) 1 0 0 forced crystal pin 35 (pal/ntsc) 1 0 1 forced crystal pin 35 (pal) 1 1 0 forced crystal pin 35 (ntsc) 1 1 1 forced secam crystal pin 35 avl level 0 automatic volume levelling not active 1 automatic volume levelling active hbl mode 0 normal blanking with horizontal blanking pulse 1 wider blanking to obtain well de?ned edges table 22 black current stabilization table 23 video identi?cation mode table 24 gain of luminance channel table 25 vertical divider mode table 26 search tuning mode table 27 video identi?cation mode table 28 long blanking mode (tda8374 and tda8375) akb stabilization 0 black-current stabilization on 1 black-current stabilization off vim video ident mode 0 video identi?cation coupled to the internal cvbs input (pin 13) 1 video identi?cation coupled to the selected cvbs input gai gain 0 normal gain of luminance channel [v 27 = 1.0 v (b-w)] 1 high gain of luminance channel [v 27 = 0.45 v (p-p)] ncin vertical divider mode 0 normal operation of the vertical divider 1 vertical divider switched to search window stm search tuning mode 0 normal operation 1 reduced sensitivity of the coincidence detector (bit sl) vid video ident mode 0 video identi?cation switches phase 1 loop on and off 1 video identi?cation not active lbm blanking mode 0 blanking adapted to standard (50 or 60 hz) 1 ?xed blanking in accordance with 50 hz standard
1997 jul 01 24 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family table 29 eht tracking mode (tda8375 and tda8377) table 30 enable vertical guard (rgb blanking) table 31 service blanking table 32 overvoltage input mode table 33 pal/ntsc or ntsc matrix (tda8374 and tda8375) table 34 pal/ntsc or ntsc matrix (tda8373 and tda8377) table 35 rgb blanking hco tracking mode 0 eht tracking only on vertical 1 eht tracking on vertical and e-w evg vertical guard mode 0 vertical guard not active 1 vertical guard active sbl service blanking mode 0 service blanking off 1 service blanking on prd overvoltage mode 0 overvoltage detection mode 1 overvoltage protection mode mat matrix 0 matrix adapted to standard (ntsc = japanese) 1 pal matrix mat matrix 0 japanese matrix 1 usa matrix rbl mode 0 blanking not active 1 blanking active table 36 noise coring peaking (tda8375 and tda8377)) table 37 enable fast blanking table 38 afc window table 39 if sensitivity table 40 modulation standard (tda8374 and tda8375) table 41 video mute table 42 sound mute cor mode 0 noise coring off 1 noise coring on ie1 fast blanking 0 fast blanking not active 1 fast blanking active afw afc window 0 normal window 1 enlarged window ifs if sensitivity 0 normal sensitivity 1 reduced sensitivity mod modulation 0 negative modulation 1 positive modulation vsw state 0 normal operation 1 if video signal switched off sm state 0 normal operation 1 sound muted
1997 jul 01 25 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family table 43 fixed audio volume table 44 demodulator frequency adjustment o utput control bits table 45 power-on-reset table 46 field frequency (tda8374 and tda8375) table 47 phase 1 lock indication table 48 x-ray protection table 49 colour decoder mode (tda8374 and tda8375) fav state 0 normal volume control 1 audio output level ?xed lfa state 0 normal if frequency 1 frequency shift for l standard por mode 0 normal mode 1 power-down mode fsi frequency 050hz 160hz sl indication 0 not locked 1 locked xpr overvoltage 0 no overvoltage detected 1 overvoltage detected cd2 cd1 cd0 standard 0 0 0 no colour standard identi?ed 0 0 1 ntsc with crystal at pin 34 0 1 0 pal with crystal at pin 35 0 1 1 secam 1 0 0 ntsc with crystal at pin 35 1 0 1 pal with crystal at pin 34 1 1 0 spare 1 1 1 spare table 50 output vertical guard table 51 indication rgb insertion table 52 output video identi?cation table 53 afc output table 54 crystal indication table 55 condition vertical divider ndf vertical output stage 0 vertical output stage ok 1 failure in vertical output stage in1 rgb insertion 0 no insertion 1 insertion ifi video signal 0 no video signal identi?ed 1 video signal identi?ed afa afb condition 0 0 outside window; too low 0 1 outside window; too high 1 0 inside window; below reference 1 1 inside window; above reference sxa sxb crystal 0 0 two 3.6 mhz crystals 0 1 one 3.6 mhz crystal 1 0 one 4.4 mhz crystal 1 1 3.6 mhz and 4.4 mhz crystals ivw video signal 0 no standard video signal detected 1 standard video signal detected (525 or 625 lines)
1997 jul 01 26 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family table 56 ic version indication limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. all pins are protected against esd by means of internal clamping diodes. 2. human body model (hbm): r = 1.5 k w ; c = 100 pf. 3. machine model (mm): r = 0 w ; c = 200 pf. quality specification in accordance with snw-fq-611e . the number of the quality specification can be found in the quality reference handbook . the handbook can be ordered using the code 9397 750 00192. latch-up i trigger 3 100 ma or 3 1.5v p(max) i trigger - 100 ma or - 0.5v p(max) . id2 id1 id0 standard 0 0 0 tda8373 0 0 1 tda8377 0 1 0 tda8374b 0 1 1 tda8374a 1 0 0 tda8374 1 0 1 tda8377a 1 1 0 tda8375a 1 1 1 tda8375 symbol parameter conditions min. max. unit v p supply voltage - 9.0 v t stg storage temperature - 25 +150 c t amb operating ambient temperature 0 70 c t sld soldering temperature for 5 s - 260 c t j operating junction temperature - 150 c v es electrostatic handling hbm; all pins; notes 1 and 2 - 2000 +2000 v mm; all pins; notes 1 and 3 - 200 +200 v
1997 jul 01 27 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family characteristics v p =8v; t amb =25 c; the pin numbers given refer to the sdip56 package; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies m ain supply ( pin 12) v p1 supply voltage 7.2 8.0 8.8 v i p1 supply current - 110 - ma p tot total power dissipation - 900 - mw h orizontal oscillator supply ( pin 37) v p2 supply voltage 7.2 8.0 8.8 v i p2 supply current - 6 - ma if circuit v ision if amplifier inputs ( pins 48 and 49) v i(rms) input sensitivity (rms value) note 1 f i = 38.90 mhz - 70 100 m v f i = 45.75 mhz - 70 100 m v f i = 58.75 mhz - 70 100 m v r i input resistance (differential) note 2 - 2 - k w c i input capacitance (differential) note 2 - 3 - pf d g v voltage gain control range 64 -- db v i(max)(rms) maximum input signal (rms value) 100 150 - mv pll demodulator (pll filter on pin 5); note 3 f pll pll frequency range 32 - 60 mhz f cr(pll) pll catching range - 2 - mhz t acq(pll) pll acquisition time -- 20 ms d f vco(t) vco frequency variation with temperature note 4 - tbf - khz/k f tune(vco) vco tuning range via the i 2 c-bus - 2.5 - mhz d f dac frequency variation per step of the dac (a0 to a6) - 20 - khz f shift(l) frequency shift with the l fa bit - 5.5 - mhz
1997 jul 01 28 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family v ideo amplifier output ( pin 6); note 5 v o zero signal output level negative modulation; note 6 - 4.7 - v positive modulation; note 6 - 2.0 - v v 6(ts) top sync level negative modulation 1.9 2.0 2.1 v v 6(w) white level positive modulation when available - 4.5 - v d v 6 difference in amplitude between negative and positive modulation - 015% z o video output impedance - 50 -w i bias internal bias current of npn emitter follower output transistor 1.0 -- ma i source(max) maximum source current -- 5ma b bandwidth of demodulated output signal at - 3db 6 9 - mhz g diff differential gain note 7 - 25% j diff differential phase notes 4 and 7 -- 5 deg nl vid video non-linearity note 8 -- 5% v clamp white spot clamp level - 5.3 - v n th(clamp) noise inverter threshold clamp level note 9 - 1.7 - v n ins noise inverter insertion level note 9 - 2.6 - v d intermodulation notes 4 and 10 blue v o = 0.92 or 1.1 mhz 60 66 - db v o = 2.66 or 3.3 mhz 60 66 - db yellow v o = 0.92 or 1.1 mhz 56 62 - db v o = 2.66 or 3.3 mhz 60 66 - db s/n signal-to-noise ratio notes 4 and 11 v i =10mv 52 60 - db at end of control range 52 61 - db v 6(rc) residual carrier signal note 4 - 5.5 - mv v 6(2h) residual 2nd harmonic of carrier signal note 4 - 2.5 - mv symbol parameter conditions min. typ. max. unit
1997 jul 01 29 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family if and tuner agc; note 12 timing of if-agc with a 2.2 m f capacitor (pin 53) modulated video interference 30% am for 1 to 100 mv; 0 to 200 hz (system b/g) -- 10 % t res(ifinc) response time to an if input signal amplitude increase of 52 db positive (when available) and negative modulation - 2 - ms t res(ifdec) response to an if input signal amplitude decrease of 52 db negative modulation - 50 - ms positive modulation (when available) - 100 - ms i 53 allowed leakage current of the agc capacitor negative modulation -- 10 m a positive modulation (when available) -- 200 na tuner take-over adjustment (via i 2 c-bus) v i(min)(rms) minimum starting level for tuner take-over (rms value) - 0.4 0.8 mv v i(max)(rms) maximum starting level for tuner take-over (rms value) 40 80 - mv tuner control output (pin 54) v oagc(max) maximum tuner agc output voltage maximum tuner gain; note 2 -- v p +1 v v o(sat) output saturation voltage minimum tuner gain; i 54 =2ma -- 300 mv i oagc(max) maximum tuner agc output swing 5 -- ma i li(rf) leakage current rf agc -- 1 m a d v i input signal variation for a control current variation of 1 ma 0.5 2 4 db afc output ( via i 2 c- bus ); note 13 res afc afc resolution - 2 - bits w sen window sensitivity 65 80 100 khz w senl window sensitivity in large window mode 195 240 300 khz v ideo identification output ( via i 2 c- bus ) t d delay time of identi?cation after the agc has stabilized on a new transmitter -- 10 ms symbol parameter conditions min. typ. max. unit
1997 jul 01 30 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family sound circuit d emodulator part v i(crpll)(rms) input limiting voltage for pll catching range (rms value) - 12mv f cr(pll) pll catching range note 14 4.2 - 6.8 mhz r i input resistance note 2 - 8.5 - k w c i input capacitance note 2 -- 5pf amr am rejection v i = 50 mv (rms); note 15 60 66 - db d e - emphasis v o(rms) output signal amplitude (rms value) note 14 - 500 - mv r o output resistance - 15 - k w v o dc output voltage - 3 - v a udio attenuator circuit v o(rms) controlled output signal amplitude (rms value) at - 6 db; note 14 500 700 900 mv v oavl(rms) output signal level when avl is activated (rms value) note 16 300 400 500 mv v ofav(rms) output signal level when fav is activated (rms value) note 14 - 500 - mv r o output resistance - 500 -w v o dc output voltage - 3.3 - v thd total harmonic distortion note 17 -- 0.5 % fav = 1; note 18 -- tbf % psrr power supply ripple rejection note 4 - tbf - db s/n int internal signal-to-noise ratio notes 4 and 19 - 60 - db s/n ext external signal-to-noise ratio notes 4 and 19 - 80 - db t dep(out) temperature dependancy of output level notes 4 and 20 -- tbf db cr control range tbf 80 tbf db vc step step size volume control - 1.5 - db control curve see fig.8 oss suppression of output signal when the mute is active - 80 - db v shift dc shift of the output level when the mute is activated - 10 50 mv e xternal audio input v i(rms) input signal amplitude (rms value) - 500 1500 mv r i input resistance - 25 - k w symbol parameter conditions min. typ. max. unit
1997 jul 01 31 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family g v(in-out) voltage gain between input and output maximum volume - 12 - db a ct crosstalk between audio signals 60 -- a utomatic volume levelling circuit (tda8373 and tda8374 only ; capacitor connected to pin 45) g max gain maximum boost; note 16 - 6 - db g min gain minimum boost -- 14 - db i att attack charge current - 1 - ma i dec decay discharge current - 200 - na v ctrl(max) control voltage maximum boost - 1 - v v ctrl(min) control voltage minimum boost - 5 - v cvbs, y/c, rgb, cd inputs and luminance input and output cvbs and y/c switch ( pins 11, 13, 17 and 38) v 11(p-p) cvbs or y input voltage (peak-to-peak value) note 21 - 1.0 1.4 v i 17 cvbs input current - 4 -m a ss cvbs suppression of non-selected cvbs input signal notes 4 and 22 50 -- db v 10(p-p) chrominance input voltage (burst amplitude) (peak-to-peak value) notes 2 and 23 - 0.3 0.45 v v 38(p-p) output signal amplitude (peak-to-peak value) - 1.0 - v z o output impedance -- 250 w v sync top sync level - 2.5 - v rgb inputs ( pins 23, 24 and 25) v 23-25(p-p) input signal amplitude for an output signal of 2 v (black-to-white) (peak-to-peak value) note 24 - 0.7 0.8 v v 23-25(p-p) input signal amplitude before clipping occurs (peak-to-peak value) note 4 1.0 -- v d v o difference between black level of internal and external signals at the outputs -- 20 mv i 23-25 input currents note 2 - 0.1 1 m a d t d delay difference for the three channels note 4 - 0 - ns f ast blanking ( pin 26) v i input voltage no data insertion -- 0.3 v data insertion 0.9 -- v v 26(max) maximum input pulse insertion -- 3.0 v symbol parameter conditions min. typ. max. unit
1997 jul 01 32 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family d t d(blank,rgb) delay difference of blanking and rgb signals note 4 -- 50 ns t sw switching speed of blanking circuit - 10 - ns i 26 input current -- 0.2 ma ss int suppression of internal rgb signals insertion; f i = 0 to 5 mhz; notes 4 and 22 - 55 - db ss ext suppression of external rgb signals no insertion; f i = 0 to 5 mhz; notes 4 and 22 - 55 - db v i input voltage to insert black level at the rgb outputs to facilitate on screen display signals being applied to the outputs 4 -- v t d(blank-rgb) delay between blanking input and rgb outputs -- 80 ns c olour difference input signals ( pins 31 and 32) v 31(p-p) input signal amplitude (r - y) (peak-to-peak value) note 2 - 1.05 - v v 32(p-p) input signal amplitude (b - y) (peak-to-peak value) note 2 - 1.35 - v i 31,32 input current for both inputs note 2 - 0.1 1.0 m a l uminance inputs and outputs ( pins 27 and 28); note 25 v 27,28 output signal amplitude (black-to-white) - 1 - v chrominance ?lters c hrominance trap circuit ; note 26 f trap trap frequency - f osc - mhz qf trap quality factor note 27 - 2 - csr colour subcarrier rejection 20 -- db f trap(secam) trap frequency during secam reception - 4.3 - mhz c hrominance band - pass circuit f c centre frequency - 1.1f osc - mhz q bp band-pass quality factor - 3 - luminance processing y delay line t d(y) delay time note 4 - 480 - ns b del(int) bandwidth of internal delay line note 4 8 -- mhz p eaking control ; note 28 t w width of preshoot or overshoot at 50% of pulse; note 8 - 160 - ns symbol parameter conditions min. typ. max. unit
1997 jul 01 33 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family s c(th) peaking signal compression threshold - 50 - ire os overshoot at maximum peaking positive - 45 - % negative - 80 - % neg/pos ratio of negative and positive overshoots - 1.8 - peaking control curve 16 steps see fig.9 n oise coring stage s coring range - 15 - ire b lack level stretcher ; note 29 bl shift(max) maximum black level shift 15 21 27 ire bl shift level shift at 100% of peak white - 1 0 +1 ire at 50% of peak white - 1 - +3 ire at 15% of peak white 6 8 10 ire horizontal and vertical synchronization and drive circuits s ync video input ( pins 11, 13 and 17) v 11,13,17 sync pulse amplitude note 2 50 300 350 mv sl hs slicing level for horizontal sync note 30 - 50 - % sl vs slicing level for vertical sync note 30 - 30 - % h orizontal oscillator f fr free running frequency - 15625 - hz d f fr spread on free running frequency -- 2% d f/ d v p frequency variation with respect to the supply voltage v p = 8.0 v 10%; note 4 - 0.2 0.5 % d f (max)(t) maximum frequency variation with temperature t amb = 0 to 70 c; note 4 -- 80 hz f irst control loop ( filter connected to pin 43); note 31 f hr(pll) holding range pll - 0.9 1.2 khz f cr(pll) catching range pll note 4 0.6 0.9 - khz s/n signal-to-noise ratio of the video input signal at which the time constant is switched - 20 - db hys hysteresis at the switching point - 1 - db s econd control loop ( capacitor connected to pin 42) dj i / dj o control sensitivity - 150 -m s/ m s t cr control range from start of horizontal output to ?yback at nominal shift position 11 12 -m s t shift horizontal shift range 63 steps 2 --m s symbol parameter conditions min. typ. max. unit
1997 jul 01 34 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family dj control sensitivity for dynamic phase compensation - 5.3 -m s/v v prot voltage to switch-on the ?ash protection note 32 6 -- v i i(prot) input current during protection -- 1ma h orizontal output ( pin 40); note 33 v ol low level output voltage i o =10ma -- 0.3 v i o(max) maximum allowed output current 10 -- ma v o(max) maximum allowed output voltage -- v p v d duty factor note 4 - 50 - % v o = high - 75 - % f sw frequency during switch-on and switch-off - 2f h - hz t sw switch-on time - 50 - ms maximum rgb drive - 100 - ms minimum rgb drive - 50 - ms f lyback pulse input and sandcastle output ( pin 41) i i(fb) required input current during the ?yback pulse note 4 100 - 300 m a v 41 output voltage during burst key 4.8 5.3 5.8 v during blanking 1.8 2.0 2.2 v v i(clamp) clamped input voltage during ?yback 2.6 3.0 3.4 v t w pulse width burst key pulse 3.3 3.5 3.7 m s vertical blanking; note 34 - 14 - lines t d(bk-sync) delay of start of burst key to start of sync 5.2 5.4 5.6 m s v ertical oscillator ; tda8373 and tda8377 operating at 60 h z ; note 35 f fr free running frequency - 50/60 - hz f lock frequency locking range 45 - 64.5 hz divider value not locked - 625/525 - lines lr locking range 488 - 722 lines/ frame v ertical ramp generator ( pins 51 and 52) v 51(p-p) sawtooth amplitude (peak-to-peak value) vs = 1fh; c=100nf;r=39k w - 3.5 - v i dch discharge current - 1 - ma i ch charge current set by external resistor note 36 - 19 -m a v slope vertical slope control range (63 steps) - 20 - +20 % symbol parameter conditions min. typ. max. unit
1997 jul 01 35 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family d i ch charge current increase f = 60 hz - 20 - % v rampl low voltage level of ramp in the normal or expand mode - 2.07 - v v ertical drive outputs ( pins 46 and 47) i o(dif)(p-p) differential output current (peak-to-peak value) va = 1fh - 0.95 - ma i cm common mode current - 400 -m a v 46,47 output voltage range 0 - 4.0 v eht tracking / overvoltage protection ( pin 50) d v 50 input voltage range 1.2 - 2.8 v m scan scan modulation range - 5 - +5 % v sen vertical sensitivity - 6.3 - %/v ew sen e-w sensitivity when switched on -- 6.3 - %/v i eq e-w equivalent output current +100 -- 100 m a v 50 overvoltage detection level note 32 - 3.9 - v d e - interlace ff d ?rst ?eld delay - 0.5h - e-w width (tda8375a, tda8377a, tda8375 and tda8377); note 37 cr control range 63 steps 100 - 65 % i eq equivalent e-w output current 0 - 700 m a v oew e-w output voltage range 1.0 - 8.0 v i oew e-w output current range 0 - 1200 m a e-w parabola / width (tda8375a, tda8377a, tda8375 and tda8377) cr control range 63 steps 0 - 22 % i eq equivalent e-w output current e-w = 3fh 0 - 440 m a e-w corner / parabola (tda8375a, tda8377a, tda8375 and tda8377) cr control range 63 steps - 43 - 0% i eq equivalent e-w output current pw = 3fh; e-w = 3fh - 190 - 0 m a e-w trapezium (tda8375a, tda8377a, tda8375 and tda8377) cr control range 63 steps - 5 - +5 % i eq equivalent e-w output current - 100 - +100 m a v ertical amplitude cr control range 63 steps; sc = 00h 80 - 120 % i eq(dif)(p-p) equivalent differential vertical drive output current (peak-to-peak value) sc = 00h 760 - 1140 m a v ertical shift cr control range 63 steps - 5 - +5 % i eq(dif) equivalent differential vertical drive output current - 50 - +50 m a symbol parameter conditions min. typ. max. unit
1997 jul 01 36 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family s- correction cr control range 63 steps 0 - 30 % v ertical expand ( zoom ) mode (tda8375 and tda8377); note 38 output current variation compared with nominal scan d i o vertical expand factor 0.75 1.38 a i o(lim) output current limiting and rgb blanking 1.08 a colour demodulation part c hrominance amplifier cr acc acc control range note 39 26 -- db d v acc change in amplitude of the output signals over the acc range -- 2db th on threshold colour killer on - 30 -- db hys off hysteresis colour killer off at strong signal conditions; s/n 3 40 db; note 4 - +3 - db at noisy input signals; note 4 - +1 - db acl circuit ; note 40 chrominance burst ratio at which the acl starts to operate - 3.0 - r eference part phase-locked loop; note 41 f cr frequency catching range 360 600 - hz dj phase shift for a 400 hz deviation of the oscillator frequency note 4 -- 2 deg oscillator tc osc temperature coef?cient of the oscillator frequency note 4 - 2.0 2.5 hz/k d f osc oscillator frequency deviation with respect to the supply v p =8v 10%; note 4 -- 250 hz r neg(min) minimum negative resistance -- 1k w c l(max) maximum load capacitance -- 15 pf h ue control cr hue hue control range 63 steps 35 40 - deg hue control curve see fig.10 symbol parameter conditions min. typ. max. unit
1997 jul 01 37 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family d hue hue variation for 10% v p note 4 - 0 - deg d hue(t) hue variation with temperature t amb = 0 to 70 c; note 4 - 0 - deg d emodulators ( pins 29 and 30) v 30(p-p) (r - y) output signal amplitude (peak-to-peak value) tda8374 and tda8375; note 42 - 0.525 - v v 29(p-p) (b - y) output signal amplitude (peak-to-peak value) tda8374 and tda8375; note 42 - 0.675 - v g gain ratio between both demodulators g (b - y) and g (r - y) 1.60 1.78 1.96 d v spread of signal amplitude ratio pal/ntsc tda8374 and tda8375; note 4 - 1 - +1 db z o output impedance between (r - y) and (b - y) note 2 - 500 -w b bandwidth of demodulators - 3 db; note 43 - 650 - khz v 29,30(p-p) residual carrier output (peak-to-peak value) f c ; (r - y) output 5 mv f c ; (b - y) output -- 5mv 2f c ; (r - y) output 5 mv 2f c ; (b - y) output -- 5mv v 30(p-p) h/2 ripple at (r - y) output (peak-to-peak value) -- 25 mv d v o(t) change of output signal amplitude with temperature note 4 - 0.1 - %/k d v o /v p change of output signal amplitude with supply voltage note 4 -- 0.1 db e j phase error in the demodulated signals note 4 -- 5 deg c olour difference matrices ( in control circuit ) tda8374 and tda8375 pal or (secam when tda8395 is applied); (r - y) and (b - y) not affected (g - y)/ (r - y) ratio of demodulated signals -- 0.51 10% - (g - y)/ (b - y) ratio of demodulated signals -- 0.19 25% - ntsc mode; the colour-difference matrix results in the following signals (nominal hue setting) (b - y) (b - y) signal 2.03/0 2.03u r (r - y) (r - y) signal 1.59/95 - 0.14u r + 1.58v r (g - y) (g - y) signal 0.61/240 - 0.31u r - 0.53v r symbol parameter conditions min. typ. max. unit
1997 jul 01 38 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family c olour difference matrices ( in control circuit ) tda8373 and tda8377 mat = 0; the colour-difference matrix results in the following signals (nominal hue setting) (b - y) (b - y) signal 2.03/0 2.03u r (r - y) (r - y) signal 1.59/95 - 0.14u r + 1.58v r (g - y) (g - y) signal 0.61/240 - 0.31u r - 0.53v r mat = 1; the colour-difference matrix results in the following signals (nominal hue setting) (b - y) (b - y) signal 1.14/ - 10 1.12u r - 0.20v r (r - y) (r - y) signal 1.14/100 - 0.20u r + 1.12v r (g - y) (g - y) signal 0.30/235 - 0.17u r - 0.25v r r eference signal output ( pin 33); note 44 f ref reference frequency - 3.58 or 4.43 - mhz v 33(p-p) output signal amplitude (peak-to-peak value) 0.2 0.25 0.3 v c ommunication with the tda8395 (tda8374 and tda8375 only ) v o output level pal/ntsc identi?ed - 1.5 - v no pal/ntsc identi?ed; secam (by tda8395) identi?ed - 5.0 - v i 31 required current to stop pal/ntsc identi?cation circuit during secam 150 --m a control part s aturation control ; note 24 ( see fig.11) cr sat saturation control range 63 steps 52 -- db c ontrast control ; note 24 ( see fig.12) cr con contrast control range 63 steps - 15 - db tracking between the three channels over a control range of 10 db -- 0.5 db b rightness control ( see fig.13) cr bri brightness control range 63 steps - 0.7 - v rgb output signals ( pins 19 to 21) v 19-21(p-p) output signal amplitude at nominal luminance input signal, nominal contrast and white point adjustment (peak-to-peak value) note 24 1.8 2.1 2.4 v v o(max)(p-p) output signal at maximum white point setting (peak-to-peak value) - 3.0 - v symbol parameter conditions min. typ. max. unit
1997 jul 01 39 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family v bw(max)(p-p) maximum signal amplitude (black-to-white) note 45 - 2.6 - v v wp(max)(p-p) maximum signal amplitude at maximum white point setting (peak-to-peak value) - 3.6 - v v red(p-p) output signal amplitude for the red channel at nominal settings for contrast and saturation control and no luminance signal to the input (r - y, pal) (peak-to-peak value) tbf 2.1 tbf v d v blank difference between blanking level measuring pulse 0.7 0.8 0.9 v t w(blank) width of the video blanking pulse when the hbl bit is active tda8375, tda8377, tda8375a and tda8377a; note 46 14.4 14.7 15.0 m s i bias internal bias current of npn emitter follower output transistor - 1.5 - ma i o available output current - 5 - ma z o output impedance - 150 -w cr bl control range of the black current stabilization at v bl = 2.5 v and nominal brightness and white-point adjustment (with respect to the measuring pulse) -- 1v v bl black level shift with picture content note 4 -- 20 mv v o(4l) output voltage of the 4-l pulse after switch-on - 4.2 - v d bl(t) variation of black level with temperature note 4 - 1.0 - mv/k d bl relative variation in black level between the three channels during variations of note 4 supply voltage ( 10%) nominal controls -- 20 mv saturation (50 db) nominal contrast -- 20 mv contrast (15 db) nominal saturation -- 20 mv brightness ( 0.5 v) nominal controls -- 20 mv temperature (range 40 c) -- 20 mv s/n signal-to-noise ratio of the output signals rgb input; note 47 60 -- db cvbs input; note 47 50 -- db v r(p-p) residual voltage at the rgb outputs (peak-to-peak value) at f osc -- 15 mv at 2f osc plus higher harmonics in rgb outputs -- 15 mv symbol parameter conditions min. typ. max. unit
1997 jul 01 40 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family notes 1. on set agc. 2. this parameter is not tested during production and is just given as application information for the designer of the television receiver. 3. loop bandwidth b l = 60 khz (natural frequency f n = 15 khz; damping factor d = 2; calculated with sync level as fpll input signal level). lc-vco circuit: q 0 3 60, c ext = 12 pf, c int =20pf. 4. this parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 5. measured at 10 mv (rms) top sync input signal. 6. so called projected zero point, i.e. with switched demodulator. b bandwidth of output signals rgb input at - 3db 8 -- mhz cvbs input at - 3 db; f osc = 3.6 mhz - 2.8 - mhz cvbs input at - 3 db; f osc = 4.44 mhz - 3.5 - mhz s-vhs input; at - 3db 5 -- mhz w hite - point adjustment i 2 c-bus setting for nominal gain hex code - 20h - g inc(max) maximum increase of the gain hex code 3fh 40 50 60 % g dec(max) maximum decrease of the gain hex code 00h 35 45 55 % b lack current stabilization ( pin 18); note 48 i bias bias current for the picture tube cathode nominal white point setting - 10 -m a i l acceptable leakage current - 100 -m a i scan(max) maximum current during scan - 0.3 - ma z i input impedance - 15 - k w b eam current limiting / vertical guard input ( pin 22); note 49 v cr contrast reduction starting voltage - 3.1 - v v difcr voltage difference for full contrast reduction - 2 - v v br brightness reduction starting voltage - 1.6 - v v difbr voltage difference for full brightness reduction - 1 - v v bias internal bias voltage - 3.3 - v z int internal impedance - 40 - k w v det detection level for vertical guard - 3.65 - v i i(min) minimum input current to activate the guard circuit - 100 -m a i i(max) maximum allowable input current - 1 - ma symbol parameter conditions min. typ. max. unit
1997 jul 01 41 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family 7. measured in accordance with the test line given in fig.14. for the differential phase test the peak white setting is reduced to 87%. a) the differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. b) the phase difference is defined as the difference in degrees between the largest and smallest phase angle. 8. this figure is valid for the complete video signal amplitude (peak white-to-black), see fig.15. 9. the noise inverter is only active in the strong signal mode (no noise detected in the incoming signal). 10. the test set-up and input conditions are given in fig.16. the figures are measured with an input signal of 10 mv (rms). 11. measured with a source impedance of 75 w , where: 12. the agc response time is also dependent on the acquisition time of the pll demodulator. the values given are valid when the pll is in lock. 13. the afc control voltage is obtained from the control voltage of the vco of the pll demodulator. the tuning information is supplied to the tuning system via the i 2 c-bus. two bits are reserved for this function. the afc value is valid only when the sl bit = 1. 14. v i = 100 mv (rms), fm: 1 khz, d f= 50 khz. 15. v i = 50 mv (rms), f = 4.5 to 5.5 mhz; fm: 70 hz, 50 khz deviation; am: 1 khz, 30% modulation. 16. the automatic volume levelling (avl) circuit automatically stabilizes the audio output signal to a certain level which can be set by means of the volume control. this avl function prevents big audio output fluctuations due to variation of the modulation depth of the transmitter. the avl can be switched on and off via the i 2 c-bus. for the tda8373 the avl is active over an input voltage range (measured at the de-emphasis output) between 75 and 750 mv (rms). for the tda8374 this input level is dependent on the crystals which are connected to the colour decoder. when only 3.5 mhz crystals are connected (indicated via the xa/xb bits) the active input level is identical to that of the tda8373. when a 4.4 mhz crystal is connected the input signal range is increased to 150 to 1500 mv (rms), this to cope with the larger fm swing of european transmitters. the avl control curve for the 2 standards is given in fig.29 and fig.30. the control range of +6 to - 14 db is valid for input signals with 50% of the maximum frequency deviation. 17. v i = 100 mv (rms), f = 5.5 mhz; fm: 1 khz, 17.5 khz deviation, 15 khz bandwidth; audio attenuator at - 6 db. 18. v i = 100 mv (rms), f = 4.5 to 5.5 mhz, fm: 1 khz, 100 khz deviation. 19. unweighted rms value, v i = 100 mv (rms), fm: 1 khz, 50 khz deviation, volume control: - 6 db. 20. audio attenuator at - 20 db; temperature range = 10 to 50 c. 21. signal with negative-going sync. amplitude includes sync pulse amplitude. 22. this parameter is measured at nominal settings of the various controls. 23. indicated as a signal for a colour bar with 75% saturation (chroma-to-burst ratio = 2.2 : 1). 24. nominal contrast is specified with the dac in position 20h. nominal saturation as maximum - 10 db. at nominal settings of brightness and white point the black level at the outputs is 300 mv lower than the level of the black current measuring pulses. 25. the luminance output and input of the tda8375a, tda8377a, tda8375 and tda8377 can be connected directly. when additional picture improvement ics (such as the tda9170) are applied the inputs of these ics must be ac-coupled because of the black level clamp requirement. the output of the picture improvement ics can be directly coupled to the luminance input as long as the dc level of the signal has a value between 1 and 7 v. to be able to apply cti ics such as the tda4565 and tda4566 the gain of the luminance channel can be increased via the setting of the gai bit in the i 2 c-bus subaddress 03. s/n = 20 log v o(b-w) v m rms () b=5mhz () ---------------------------------------------------------
1997 jul 01 42 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family 26. when the colour decoder is forced to a fixed subcarrier frequency (via the xa/xb or the cm bits) the chroma trap is always switched on, also when no colour signal is identified. when 2 crystals are active the chroma trap is switched off when no colour signal is identified. 27. the - 3 db bandwidth of the circuit can be calculated using the following equation: 28. valid for a signal amplitude on the y input of 0.7 v (black-to-white) (100 ire) with a rise time (10% to 90%) of 70 ns and the video switch in the y/c mode. during production the peaking function is not tested by measuring the overshoots but by measuring the frequency response of the y output. 29. for video signals with a black level which deviates from the back porch blanking level the signal is stretched to the blanking level. the amount of correction depends on the ire value of the signal (see fig.17). the black level is detected by means of an external capacitor. the black level stretcher can be made inoperative by connecting the pin to ground. the values given are valid only when the luminance input signal has an amplitude of 1 v (p-p). 30. the slicing level is independent of sync pulse amplitude. the given percentage is the distance between the slicing level and the black level (back porch). when the amplitude of the sync pulse exceeds the value of 350 mv the sync separator will slice the sync pulse at a level of 175 mv above top sync. the maximum sync pulse amplitude is 4 v (p-p). 31. to obtain a good performance for both weak signal and vcr playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the bus. therefore the circuit contains a noise detector and the time constant is switched to slow when too much noise is present in the signal. in the fast mode, during the vertical retrace time, the phase detector current is increased by 50% so that phase errors due to the head switching of the vcr are corrected as soon as possible. switching between the two modes can be made automatically or overruled by the bus (see tables 4, 6, 8 and 10). the circuit contains a video identification circuit which is independent of first loop. this identification circuit can be used to close or open the first control loop when a video signal is present or not on the input. this ensures a stable on-screen-display (osd) when just noise is present at the input. the coupling of the video identification circuit with the first loop can be overruled via the i 2 c-bus. the coupling between the phase 1 detector and the video identi?cation circuit is only active for internal cvbs signals. to prevent the horizontal synchronization being disturbed by anti-copy guard signals, such as macrovision, the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. the width of the gate pulse is approximately 22 m s. furthermore the phase detector is gated during the lower part of the picture (pulse width = 12 m s) to prevent disturbances due to overmodulated subtitles. the latter gating is active only with standard signals (number of lines per frame 625 or 525). during weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to 5.7 m s so that the effect of the noise is reduced to a minimum. the output current of the phase detector in the various conditions are given in table 57. 32. the ics have 2 protection inputs. the protection at pin 42 is intended to be used as flash protection. when this protection is activated the horizontal drive is switched off immediately and then switched on again via the slow start procedure. the protection on pin 50 is intended for overvoltage (x-ray) protection. when this protection is activated the horizontal drive can be switched off directly (via the slow stop procedure). it is also possible to continue the horizontal drive and to set the protection bit (xpr) in the output bytes of the i 2 c-bus. the choice between the 2 modes of operation is made with the prd bit. f 3db C f osc 1 1 2q ------- - C ? ?? =
1997 jul 01 43 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family 33. during switch-on the horizontal output starts with twice the frequency and with a duty cycle of 75% (v o = high). after approximately 50 ms the frequency is changed to the normal value. because of the high frequency the peak currents in the horizontal output transistor are limited. also during switch-off the frequency is switched to twice the value and the rgb drive is set to maximum so that the eht capacitor is discharged. this switching to maximum drive occurs only when rbl = 0, for rbl = 1 the drive voltage remains minimum during switch-off. after approximately 100 ms the rgb drive is set to minimum and 50 ms later the horizontal drive is switched off. the horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched on during the flyback time. 34. the vertical blanking pulse in the rgb outputs has a width of 26 or 21 lines (50 or 60 hz system). the width of the vertical sync pulse in the sandcastle pulse has a width of 14 lines. this to prevent a phase distortion on top of the picture due to timing modulation of the incoming flyback pulse. 35. the timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. this divider circuit has 3 modes of operation. a brief explanation is given below. for the tda8373 and tda8377 only the 60 hz figures are valid. a) search mode large window: this mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per frame in the 50 hz mode is between 311 and 314 and in the 60 hz mode between 261 and 264) is received. in the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 hz). b) standard mode narrow window: this mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window. when the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. consequently, the disturbance of the picture is very small. the circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. c) standard tv-norm (divider ratio 525 (60 hz) or 625 (50 hz): when the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in accordance with the tv-norm. when 15 standard tv-norm pulses are counted the divider system is switched to the standard divider ratio mode. in this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. when 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window. the vertical divider needs some waiting time during channel-switching of the tuner. when a fast reaction of the divider is required during channel-switching the system can be forced to the search window by means of the ncin bit in subaddress 08. 36. conditions: frequency is 60 hz; normal mode; vs = 1f. 37. the output range percentages mentioned for e-w control parameters are based on the assumption that 400 m a variation in e-w output current is equivalent to 20% variation in picture width. because of the horizontal and vertical zoom feature in the tda8375 and tda8377 (see also note 38) the e-w width control range is increased compared with previous ics such as the tda8366. the increased e-w width control is also available in the tda8375a and tda8377a although these devices do not have the vertical zoom feature. 38. the tda8375 and tda8377 have a zoom adjustment possibility for the vertical and horizontal deflection. for this reason an extra dac has been added in the vertical amplitude control which controls the vertical scan amplitude between 0.75 and 1.38 of the nominal scan. at an amplitude of 1.08 of the nominal scan the output current is limited and the blanking of the rgb outputs is activated (see fig.28). in addition to the variation of the vertical amplitude the vertical slope control range is also increased. this gives the possibility to vary the position of the bottom part of the picture independent from the upper part. the nominal scan height must be adjusted at a position of 19h of the vertical zoom dac
1997 jul 01 44 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family 39. at a chrominance input voltage of 660 mv (p-p) [colour bar with 75% saturation i.e. burst signal amplitude 300 mv (p-p)] the dynamic range of the acc is +6 and - 20 db. 40. the acl function is available in the ntsc devices and is active in the pal/ntsc devices when ntsc signals are received. the acl circuit reduces the gain of the chroma amplifier for input signals with a chroma-to-burst ratio which exceeds a value of 3.0. 41. all frequency variations are referenced to 3.58 or 4.43 mhz carrier frequency. all oscillator specifications are measured with the philips crystal series 9922 520 with a series capacitor of 18 pf. the oscillator circuit is rather insensitive to the spurious responses of the crystal. as long as the resonance resistance of the 3rd overtone is higher than that of the fundamental frequency the oscillator will operate at the correct frequency. typical parameters for the above mentioned crystals are as follows: a) load resonance frequency f 0 = 4.433619 or 3.579545 mhz (c l = 20 pf). b) motional capacitance c mot = 20.6 ff (4.43 mhz crystal) or 14.7 ff (3.58 mhz crystal). c) parallel capacitance c par = 5 pf for both crystals. the minimum detuning range can only be specified if both the ic and the crystal tolerances are known and the figures given are therefore valid for the specified crystal series. in this figure tolerances of the crystal with respect to nominal frequency, motional capacitance and ageing have been taken into account and have been counted for gaussian addition. whenever different typical crystal parameters are used the following equation might be helpful for calculating the impact on the detuning capabilities: the detuning range divided by the resulting detuning range should be corrected for temperature shift and supply deviation of both the ic and the crystal. the actual series capacitance in the application should be c l = 18 pf to account for parasitic capacitances on and off chip. for 3-norma applications with 2 crystals connected to one pin the maximum parasitic capacitance of the crystal pin should not exceed 15 pf. 42. the (r - y) and (b - y) signals are demodulated with a phase difference of the reference carrier of 90 and a gain ratio . the output signal amplitudes of the tda8373 and tda8377a have twice the value. this is necessary to compensate for the gain of the baseband delay line (tda4665). the matrixing to the required signals is realized in the control part. 43. this parameter indicates the bandwidth of the complete chrominance circuit including the chrominance band-pass filter. the bandwidth of the low-pass filter of the demodulator is approximately 1 mhz. 44. the sub-carrier output signal can be used as reference signal of external comb filter ics (all ics) and as a reference signal for the secam decoder tda8395 (only tda8374 and tda8375). in the latter types the output signal is continuously available when pal or ntsc signals are detected. when the system identifies a secam signal the reference signal is only present in the vertical retrace period. this to prevent interference between the reference signal and the secam input signal. for comb filter applications the dc load on this pin should be limited to 50 m a to avoid problems with secam identification. 45. at nominal setting of the gain control. when this amplitude is exceeded the signal will be clipped. 46. when the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realized by means of a reduction of the horizontal scan amplitude, the edges of the picture may be slightly disturbed. this effect can be prevented by adding additional blanking to the rgb signals. this blanking pulse is derived from the horizontal oscillator and is directly related to the incoming video signal (independent of the flyback pulse). the additional blanking overlaps the normal blanking signal with approximately 1 m s on both sides. this blanking is activated with the hbl bit (only in the tda8375 and tda8377). 47. signal-to-noise ratio (s/n) is specified as a peak-to-peak signal with respect to rms noise (bandwidth 5 mhz). c mot 1 c par c l ----------- + ? ? ?? 2 ------------------------------ - by C () ry C () - ------------------- - 1.78 =
1997 jul 01 45 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family 48. this is a current input. the indicated value of the nominal bias current is obtained at the nominal setting of the gain (white point) control. the actual value of the bias current depends on the gain control setting of each channel. as a result the black current of each gun is adapted to the white point setting so that the background colour will follow the white point adjustment. 49. the beam current limiting and the vertical guard function have been combined on this pin. the beam current limiting function is active during the vertical scan period. table 57 output current of the phase detector in the various conditions note 1. during vertical retrace the width is 22 m s and during the lower part of the picture 12 m s. in the other conditions the width is 5.7 m s and the gating is continuous. i 2 c-bus commands ic conditions j -1 current/mode vid poc foa fob ident coin noise scan v-retr gating mode - 0 0 0 yes yes no 180 270 yes (1) auto - 0 0 0 yes yes yes 30 30 yes auto - 0 0 0 yes no - 180 270 no auto - 0 0 1 yes yes - 30 30 yes slow - 0 0 1 yes no - 180 270 no slow - 0 1 0 yes yes no 180 270 yes fast - 0 1 0 yes yes yes 30 30 yes slow -- 11 --- 180 270 no fast 00 -- no -- 6 6 no osd - 1 -------- off fig.8 volume control curve. handbook, halfpage mgk290 0 0 - 20 - 40 - 60 - 80 - 100 10 (db) dac (hex) 20 30 40 fig.9 peaking control curve. positive overshoot. handbook, halfpage 0 0 10 20 30 40 4 (%) dac (hex) 8c10 f mgk291
1997 jul 01 46 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.10 hue control curve. handbook, halfpage 0 - 40 - 20 40 20 0 10 (deg) dac (hex) 20 30 40 mgk292 fig.11 saturation control curve. handbook, halfpage 0 0 300 250 200 150 100 50 10 (%) dac (hex) 20 30 40 mgk293 fig.12 contrast control curve. handbook, halfpage mgk294 0 100 80 60 40 20 (%) 010 dac (hex) 20 30 40 fig.13 brightness control curve. relative variation with respect to the measuring pulse. handbook, halfpage mgk295 0 0.7 0.35 - 0.35 0 - 0.7 10 (v) dac (hex) 20 30 40
1997 jul 01 47 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family mbc212 100% 92% 30% 16 % for negative modulation 100% = 10% rest carrier fig.14 video output signal. handbook, full pagewidth mbc211 100% 86% 72% 58% 44% 30% 64 60 56 52 48 44 40 36 32 22 12 10 26 m s fig.15 test signal waveform.
1997 jul 01 48 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family handbook, full pagewidth mbc213 sc cc pc 30 db 13.2 db 3.2 db sc cc pc 30 db 13.2 db 10 db blue yellow fig.16 test set-up intermodulation. input signal conditions: sc = sound carrier; cc = colour carrier; pc = picture carrier. all amplitudes with respect to top sync level. value at 0.92 or 1.1 mhz 20 log v o at 3.58 or 4.4 mhz v o at 0.92 or 1.1 mhz ------------------------------------------------------------ 3.6 db + = value at 2.66 or 3.3 mhz 20 log v o at 3.58 or 4.4 mhz v o at 2.66 or 3.3 mhz ------------------------------------------------------------ = mbc210 attenuator spectrum analyzer test circuit cc pc sc s gain setting adjusted for blue
1997 jul 01 49 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family test and application information fig.17 input/output relationship of the black level stretcher. handbook, halfpage a a b 40 80 100 60 20 0 100 20 0 40 - 20 60 80 mgk297 in (ire) out (ire) b a-a = maximum black level shift; b-b = level shift at 15% of peak white. fig.18 simplified application diagram. handbook, full pagewidth mgk302 3.5 mhz 4.4 mhz saw filter from tuner tda8395 tda837x tda4665 band- pass trap 4316 11 54 50 51 39 47 48 57 46 45 35 36 37 38 10 27 17 18 58 59 21 20 24 29 33 32 31 62 63 64 56 30 34
1997 jul 01 50 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family east-west output stage in order to obtain correct tracking of the vertical and horizontal eht correction, the e-w output stage should be dimensioned as illustrated in fig.19. resistor r ew determines the gain of the e-w output stage. resistor r c determines the reference current for both the vertical sawtooth generator and the geometry processor. the preferred value of r c is 39 k w which results in a reference current of 100 m a (v ref = 3.9 v). the value of r ew must be: example: with v ref = 3.9 v; r c =39k w and v scan = 120 v then r ew ? 68 k w . control ranges of geometry control parameters typical case curves; r c =39k w , c saw = 100 nf. figures 20 to 23 are valid for all types. figures 24 to 27 are valid for tda8375 and tda8377. r ew r c v scan 18 v ref ---------------------- - = fig.19 east-west output stage. handbook, full pagewidth tda8375 tda8377 52 51 45 diode modulator mgk300 100 nf (5%) c saw 39 k w (2%) r c r ew v ref v ew v supply e-w output stage horizontal deflection stage e-w drive v scan
1997 jul 01 51 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.20 control range of vertical amplitude. va = 0, 31h and 63h; vsh = 31h; sc = 0. handbook, halfpage 0 - 400 t time 200 - 200 400 - 600 600 0 1 / 2 t mgh366 i vert ( m a) fig.21 control range of vertical slope. vs = 0, 31h and 63h; va = 31h; vhs = 31h; sc = 0. handbook, halfpage 0 - 500 t time 100 - 300 - 100 300 - 700 500 1 / 2 t mgh367 i vert ( m a) fig.22 control range of vertical shift. vsh = 0, 31h and 63h; va = 31h; sc = 0. handbook, halfpage 0 - 400 t time 200 - 200 400 - 600 600 0 1 / 2 t mgh368 i vert ( m a) fig.23 control range of s-correction. sc = 0, 31h and 63h; va = 31h; vhs = 31h. picture height does not change with s-correction for nominal vertical amplitude (va = 31). handbook, halfpage 0 - 400 t time 200 - 200 400 - 600 600 0 1 / 2 t mgh369 i vert ( m a)
1997 jul 01 52 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.24 control range of e-w width. ew = 0, 31h and 63h; pw = 31h; cp = 31h. handbook, halfpage 0 200 t time 800 400 1000 600 1200 0 1 / 2 t mbk039 i ew ( m a) fig.25 control range of e-w parabola/width ratio. pw = 0, 31h and 63h; ew = 31h; cp = 31h. handbook, halfpage 0t time 800 300 600 400 700 500 900 1 / 2 t mbk040 i ew ( m a) fig.26 control range of e-w corner/parabola ratio. cp = 0, 31h and 63h; ew = 31h; pw = 63h. handbook, halfpage 0t time 800 300 600 400 700 500 900 1 / 2 t mbk041 i ew ( m a) fig.27 control range of e-w trapezium correction. tc = 0, 31h and 63h; ew = 31h; pw = 31h; cp = 0. handbook, halfpage 0t time 300 600 400 700 500 1 / 2 t mbk042 i ew ( m a)
1997 jul 01 53 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family adjustment of geometry control parameters the deflection processor of the tda8373 and tda8374 offers 5 control parameters for picture alignment: vertical picture alignment C s-correction C vertical amplitude C vertical slope C vertical shift C horizontal shift alignment. the tda8375, tda8377, tda8375a and tda8377a offer in addition the following functions for horizontal alignment: e-w width e-w parabola/width e-w corner/parabola e-w trapezium correction. it is important to notice that the ics are designed for use with a dc-coupled vertical deflection stage. this is the reason why a vertical linearity alignment is not necessary (and, therefore, not available). for a particular combination of picture tube type and vertical output stage and e-w output stage, it is determined which are the required values for the settings of s-correction. these parameters can be preset via the i 2 c-bus and do not need any additional adjustment. the remainder of the parameters are preset with the mid-value of their control range (i.e. 1fh), or with the values obtained by previous tv set adjustments. the vertical shift control is intended for compensation of off-sets in the external vertical output stage or in the picture tube. it can be shown that without compensation these off-sets will result in a certain linearity error, especially with picture tubes that need large s-correction. the total linearity error is in 1st order approximation proportional to the value of the off-set and to the square of the s-correction needed. the necessity to use the vertical shift alignment depends on the expected off-sets in vertical output stage and picture tube, on the required value of the s-correction and on the demands upon vertical linearity. for adjustment of the vertical shift and vertical slope independent of each other, a special service blanking mode can be entered by setting the sbl bit high. in this mode the rgb outputs are blanked during the second half of the picture. there are 2 different methods for alignment of the picture in vertical direction. both methods make use of the service blanking mode. the first method is recommended for picture tubes that have a marking for the middle of the screen. with the vertical shift control the last line of the visible picture is positioned exactly in the middle of the screen. after this adjustment the vertical shift should not be changed. the top of the picture is placed by adjusting the vertical amplitude and the bottom by adjusting the vertical slope. the second method is recommended for picture tubes that have no marking for the middle of the screen. for this method a video signal is required in which the middle of the picture is indicated (e.g. the white line in the circle test pattern). with the vertical slope control the beginning of the blanking is positioned exactly on the middle of the picture. then the top and bottom of the picture are placed symmetrically with respect to the middle of the screen by adjustment of the vertical amplitude and vertical shift. after this adjustment the vertical shift has the correct setting and should not be changed. if the vertical shift alignment is not required vsh should be set to its mid-value (i.e. vsh = 1fh). the top of the picture is then placed by adjusting the vertical amplitude and the bottom by adjusting the vertical slope. after the vertical picture alignment the picture is positioned in the horizontal direction by adjusting the horizontal shift. to obtain the full range of the vertical zoom function with the tda8375 and tda8377 the adjustment of the vertical geometry should be carried out at a nominal setting of the zoom dac at position 19h.
1997 jul 01 54 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.28 sawtooth waveform and blanking pulse of the tda8375 and tda8377. handbook, full pagewidth 70 60 50 40 75% 100% 138% 30 20 10 0 - 10 - 20 - 30 - 40 - 50 - 60 time top picture bottom picture blanking for exponential 138% t 1/2 t vertical position (%) mgk296 fig.29 avl characteristics of the tda8373 and tda8374 for 3.5 mhz standard. handbook, halfpage 10 4 10 3 10 2 mgk298 10 10 2 10 3 10 4 audio output (mv) (rms) de-emphasis (mv) (rms) c 25 khz (norm) b a 6 db d avl on avl off 14 db see table 58.
1997 jul 01 55 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family table 58 explanation to fig.29 table 59 explanation to fig.30 a b c d description 50 100 250 500 de-emphasis pin 55 [mv (rms)] 5 10 25 50 fm swing (khz) 50 100 250 500 avl input [mv (rms)] 100 200 500 1000 external input [mv (rms)] a b c d description 100 200 250 1000 de-emphasis pin 55 [mv (rms)] 10 20 25 100 fm swing (khz) 50 100 125 500 avl input [mv (rms)] 100 200 250 1000 external input [mv (rms)] fig.30 avl characteristics of the tda8374 for 4.4 mhz standard. handbook, halfpage 10 4 10 3 10 2 mgk299 10 10 2 10 3 10 4 audio output (mv) (rms) de-emphasis (mv) (rms) c 50 khz (norm) b a e d avl on avl off 6 db 14 db see table 59.
1997 jul 01 56 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family internal pin configuration fig.31 pin 1. mgk303 1 tstcon 2.2 k w 300 w 10 pf sound limiter plus demodulator 15 k w 15 k w 15 pf fig.32 pin 2. mgk304 2 100 w 4 v sound switch plus amplifier 25 k w + fig.33 pins 3, 4 and 5. mgk305 3 4 5 6 k w 6 k w ++ + + fig.34 pin 6. mgk306 6 200 w ++ fig.35 pin 7. mgk343 300 w 5 v 7
1997 jul 01 57 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.36 pin 8. mgk307 300 w 30 w 5 v 8 fig.37 pin 9. mgk308 ++ 9 fig.38 pin 10. mgk309 30 k w 100 k w 100 k w decoder pip txt 10 pf 10 tstcon 300 w + v ref fig.39 pins 11, 13 and 17. mgk310 100 w + decoder chroma switch output decoder luma sync switch control dummy clamp 11, 13, 17 fig.40 pins 12 and 37. mgk344 + analog supply 12, 37 fig.41 pin 14. mgk333 + 14 gnd1
1997 jul 01 58 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.42 pin 15. mgk312 15 2 k w 300 w sound amplifier 100 m a + + fig.43 pin 16. mgk313 16 50 k w 300 w - 100 m a/ + 100 m a 10 pf filter tuning + fig.44 pin 18. mgk314 10 pf i l v ref = 4 v 200 m a 10 m a 18 14 k w + v/i fig.45 pins 19, 20 and 21. mgk315 100 w + + 2 ma 19, 20, 21 fig.46 pin 22. mgk316 peak white limiting v ref1 v ref2 200 m a + + 22 1 k w 40 k w + brightness control contrast control 4 v vertical guard
1997 jul 01 59 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.47 pins 23, 24 and 25. mgk317 50 m a 300 w + + + + 6 v 23, 24, 25 fig.48 pin 26. mgk318 + + 26 300 w + 4 v insertion blanking fig.49 pin 27. mgk319 10 w 50 pf 0.2 m a + + + + 6 v 27 fig.50 pin 28. mgk320 28 10 w 500 m a + + 500 w fig.51 pins 29 and 30. mgk321 100 w + + + 29, 30 fig.52 pins 31 and 32. mgk322 ++ 100 w 2.5 v 31, 32
1997 jul 01 60 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.53 pin 33. mgk323 33 2.7 v 30 w 250 m a ++ fig.54 pins 34 and 35. mgk324 + + r r 3.7 v pin 34: crystal = 3.58 mhz; r = 1 k w pin 35: crystal = 4.43 mhz; r = 1 k w 34, 35 fig.55 pin 36. mgk325 36 + + + 100 w 3.8 v fig.56 pin 38. mgk326 + + 400 w 600 m a 38 100 w tstcon fig.57 pin 39. mgk327 + 39 fig.58 pin 40. mgk328 40 30 w + protection
1997 jul 01 61 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.59 pin 41. mgk329 2 m a 41 + + + 30 w j burstkey burstkey v blank 5.3 v 3 v 2.9 v fig.60 pin 42. mgk330 300 w 42 + + 5.3 v + flash level fig.61 pin 43. mgk331 43 hosc 300 w 300 w + + j 3.3 v 4.7 v (nc plus por) 4 v 4 v df
1997 jul 01 62 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.62 pin 44. mgk311 44 gnd2, connected to substrate fig.63 pin 45. mgk332 45 + 600 w fig.64 pins 46 and 47. mgk334 + 46, 47 fig.65 pins 48 and 49. mgk335 100 w 1 k w 1 k w 100 w 48 2.4 pf 49 + + ++ to if amplifier fig.66 pin 50. mgk336 300 w 50 j + 2 v + j 3.9 v xpr fig.67 pin 51. mgk337 51 + + j
1997 jul 01 63 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.68 pin 52. mgk338 i ref v ref 52 + fig.69 pin 53. mgk339 + + 53 + clamp 1.5 ma 50 m a 600 m a 500 na gating agc det lspeed negmod fig.70 pin 54. mgk340 54 tstcon fig.71 pin 55. mgk341 55 sound switch plus amplifier sound demodulator ++ 3 v 20 k w
1997 jul 01 64 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family fig.72 pin 56. mgk342 56 dc stabilisation + 100 m a - 50/50 m a
1997 jul 01 65 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family package outlines unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.36 0.10 2.87 2.57 0.25 0.50 0.35 0.25 0.13 14.1 13.9 1 18.2 17.6 1.43 1.23 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot319-1 92-11-17 95-02-04 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.2 0.8 d b p e q e a 1 a l p q detail x l (a ) 3 b 19 y c d h b p e h a 2 v m b d z d a z e e v m a w m 1 64 52 51 33 32 20 x w m 0 5 10 mm scale pin 1 index 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height qfp64: plastic quad flat package; sot319-1 a max. 3.3
1997 jul 01 66 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot400-1 95-12-06 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 52.4 51.6 14.0 13.6 3.2 2.8 0.18 1.778 15.24 15.80 15.24 17.15 15.90 2.3 5.08 0.51 4.0 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z 56 1 29 28 b e pin 1 index a max. 12 a min. a max. sdip56: plastic shrink dual in-line package; 56 leads (600 mil) sot400-1
1997 jul 01 67 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). sdip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. qfp r eflow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary from 50 to 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheat for 45 minutes at 45 c. w ave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 jul 01 68 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. short-form speci?cation the data in this speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 jul 01 69 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family notes
1997 jul 01 70 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family notes
1997 jul 01 71 philips semiconductors preliminary speci?cation i 2 c-bus controlled economy pal/ntsc and ntsc tv-processors tda837x family notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca54 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 547047/1200/01/pp72 date of release: 1997 jul 01 document order number: 9397 750 01808

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